(a) Field of the Invention
The present invention relates to a reference voltage generation circuit for use in a semiconductor device, and more particularly, to a reference voltage generation circuit for providing a stable output voltage therefrom over a wide voltage range of the power source for the reference voltage generation circuit.
(b) Description of the Related Art
A reference voltage generation circuit is used in various kinds of semiconductor devices in order to stabilize circuit operation and semiconductor characteristics. For example, because of need for a voltage higher than a source voltage or need for a negative voltage, a nonvolatile memory device includes a booster circuit having a voltage regulating circuit so as to output a constant voltage. The reference voltage generation circuit is used in the voltage regulating circuit as a reference voltage source.
In the nonvolatile memory device, if an output voltage from the reference voltage generation circuit varies, the variation is amplified in the voltage regulating circuit, resulting in significant variation in an output voltage from the voltage regulating circuit. Since the output voltage of the voltage regulating circuit determines, for example, the amount of electrons to be injected into the floating gate of a nonvolatile memory cell, a reduction in the output voltage causes a reduction in the amount of electrons injected, thereby affecting the data holding characteristic of the nonvolatile memory device. In other words, variation in the output voltage of the reference voltage generation circuit impairs the reliability of the nonvolatile memory device.
Further, the reference voltage generation circuit determines the amount of current flowing through the internal circuits of a semiconductor device. Thus, variation in the output voltage of the reference voltage generation circuit causes significant variation in the current dissipation of the entire semiconductor device. Since a semiconductor device having current dissipation which does not meet a product standard or specification is rejected in a test, variation in the output voltage of the reference voltage generation circuit may impair the yield of semiconductor devices.
FIG. 1 is a circuit diagram of a conventional reference voltage generation circuit using a bandgap voltage of diode. The reference voltage generation circuit includes the following elements: a first current mirror circuit CM1 which includes p-channel transistors P1, P2, and P3, among which the transistor P2 is disposed on the reference side; a second current mirror circuit CM4 which includes n-channel transistors N1 and N2 connected in series with the transistors P1 and P2, respectively, and in which the transistor N1 is disposed on the reference side; a diode D1 connected in series with the transistors P1 and N1; a resistor R1 and a diode D2 connected in series with the transistors P2 and N2; and a resistor R2 and a diode D3 connected in series with the transistor P3.
The transistors P1, P2, and P3 have the same design dimension, and the transistors N1 and N2 have the same design dimension. An output voltage Vout is determined from a current Io output from the transistor P3 and the resistor R2. The diodes D2 and D3 are each composed of a plurality of (N) diodes that have the same design dimension as the diode D1 and are connected in parallel with one another.
The respective source terminals of the transistors P1 and P2 are connected to a voltage source Vdd, and the respective gate terminals of the transistors P1 and P2 are connected together. Accordingly, the transistors P1 and P2 are identical in drain current and gate-to-source voltage. Since the respective gate terminals of the transistors N1 and N2 are connected together, the transistors N1 and N2 have the same gate voltage. Assuming that the transistors N1 and N2 have the same dimensions, the transistors N1 and N2 have the same threshold voltage, which provides the same source potential therebetween. The bandgap voltages of the diodes D1 and D2 provide following expression. EQU R1(I.sub.0 +(kT/q)ln(I.sub.0 /I.sub.SD2)=(kT/q)ln(I.sub.0 /I.sub.SD1)
where I.sub.0 is a current flowing through the transistors P1, P2, and P3, I.sub.SD1 and I.sub.DS2 are the respective saturation currents of the diodes D1 and D2; T is an absolute temperature; k is a Boltzman constant; and q is the charge of an electron.
The above expression is arranged to the expression given in terms of Io as follows: EQU Io=(1/R1).times.(kT/q).times.lnN (1)
Wherein N is the number of diodes D1.
Thus, the output voltage Vout is expressed by EQU Vout=.chi.R1.times.Io+(kT/q).times.ln(I.sub.0 /N.multidot.I.sub.SD1)
Wherein .chi.=R2/R1.
By substitution of Expression (1) into the above expression, Vout is expressed by EQU Vout=(kT/q).times.[(.chi.-1)lnN+ln{(kT/q)/R1.multidot.I.sub.SD1)}+ln (lnN)}] (2)
When the respective nodes connected to the drains of the transistors P1, P2, and P3 are represented by nodes A, B, and C, the potential at node A is the sum of threshold voltage Vtn of the transistor N1 and forward voltage drop VD1 of the diode D1; the potential at node B is equal to a value obtained through the subtraction of threshold voltage Vtp of the transistor P2 from the source voltage Vdd; and the potential at node C is Vout as represented by Expression (2).
Even when the source voltage Vdd for the reference voltage generation circuit varies, the source-to-drain voltage Vsd of the transistor N1 and that of the transistor P2 remain substantially unchanged; however, the respective source-to-drain voltages Vsd of the transistors P1, P3, and N2 vary in association with variation in the source voltage Vdd. That is, the current I.sub.0 flowing through current paths of each of the current mirror circuits CM1 and CM4 and the output voltage Vout vary in association with variation in the source voltage Vdd. As mentioned previously, variation in the reference voltage causes various drawbacks in semiconductor devices. Thus, variation in the output of the reference voltage generation circuit should be suppressed to a small magnitude.
FIG. 2 is a graph showing a voltage-current characteristic of an ordinary transistor, measured in a sate in which the gate-to-source voltage Vgs is fixed to a certain level. In FIG. 2, the Y axis represents a drain current Id, and the X axis represents the source-to-drain voltage Vsd. In a transistor, as the source-to-drain voltage Vsd increases with the gate-to-source voltage Vgs fixed at a certain level, the drain current Id increases. As a channel length (a distance between the source and the drain) L of a MOS transistor decreases, the amount of an increase in the drain current Id increases. This is because, as the channel length L decreases, the influence of the expansion of a depletion layer increases significantly.
FIG. 3 is a graph showing variation in drain current accompanying variation in the source voltage Vdd for the reference voltage generation circuit. When an output current I.sub.2 is determined by the transistors N1 and N2, the source-to-drain voltage Vsd of the transistor P2, which is connected to function as a diode, is determined. The gate voltage of the transistor P3 is also determined. When the source voltage Vdd varies, the source-to-drain voltage Vsd of the transistor P3 increases. In this case, if the channel length L is relatively short, the output current varies significantly from I.sub.2 to I.sub.3.
In the reference voltage generation circuit, variation in output current due to variation in source voltage can be suppressed to a small magnitude by increasing the channel length L, as shown in FIG. 2. However, when the channel length L is increased, a channel width W must be increased accordingly in order to maintain the transconductance of the transistor unchanged, causing a problem in that the surface area of a chip increases.